1. Field of the Invention
This invention relates generally to FIFO memories, and more particularly to a fast reprogrammable FIFO status flags system.
2. Description of the Prior Art
Technology continues to provide data processing and communication devices that transmit and process data at ever increasing speeds. In order to accommodate this increased data transmission and data processing speeds, there is a need to provide a fast reprogrammable FIFO status flags system. These status flags should be capable of switching in a short amount of time and should be capable of being reprogrammed in a short amount of time subsequent to FIFO write and read operations.
Most, if not all, stand-alone FIFO memories produced today employ status flag outputs which indicate the degree of xe2x80x9cfullnessxe2x80x9d or number of data words stored relative to the maximum FIFO capacity. Most of these FIFOs are equipped with one or more programmable status flags, which the user can program to detect specific numbers of stored words. In view of the changing data communication technology, there is a need for a pair of these status flags which can switch in a short amount of time relative to an external clock and that can be reprogrammed multiple times, even after FIFO writes and reads have occurred, as stated above.
U.S. Pat. No. 5,084,841, entitled Programmable Status Flag Generator FIFO Using Gray Code, issued Jan. 28, 1992 to Williams, et al., and assigned to the assignee of the present invention, discloses generating programmable status flags by comparing various gray-code write and read counter outputs and using those compare results to set and reset some latches which then become the status flag outputs. U.S. Pat. No. 5,084,841 is incorporated by reference herein in its entirety. The technique disclosed by the ""841 patent provides for reprogramming the status flag outputs subsequent to a reset operation. To further accommodate the foregoing discussed increased data transmission and data processing speeds, it would be advantageous if the programmable FIFO status flag technique could allow reprogramming of status flag outputs an unlimited number of times subsequent to FIFO writes and reads.
Other known techniques that accommodate programming FIFO status flags use binary write and read counters preset to fixed values, and then subtract one count from the other. The resulting difference is compared to values stored in user-programmable registers; and the compare results become the status flags. Propagation delays to the flag outputs for such systems include the delay through the subtraction logic and additional delays associated with filtering out glitches caused by multiple counter outputs switching in the same cycle. These other known techniques therefore suffer from undesirable and disadvantageous propagation delays.
In view of the foregoing, there is a need for a fast reprogrammable FIFO status flags system that is capable of being reprogrammed an unlimited number of times, even after FIFO writes and reads have occurred, and that has inherent propagation delay times substantially shorter than that associated with known systems.
The present invention is directed to a fast reprogrammable FIFO status flags system that is capable of being reprogrammed an unlimited number of times, even after FIFO writes and reads have occurred, and that has inherent propagation delay times substantially shorter than that associated with known systems. According to one embodiment, the reprogrammable FIFO status flags system includes a FLAG_GEN block, a WRITE/READ OFFSETS block and an OFFSET_GEN block. The FLAG_GEN block generates signals PAE (programmable almost empty) and PAF (programmable almost full). Two offset values (xe2x80x98Nxe2x80x99 and xe2x80x98Mxe2x80x99) are programmed into the FIFO. PAE is high only when the number of words stored in the FIFO equals N or fewer. PAF is high only when the number of words stored in the FIFO equals D minus M or more where D is the FIFO depth, e.g. 4096 words. Read and write counter values are incremented using a gray-code sequence in which only one bit is different between any two consecutive states to prevent comparator decoding glitches. Propagation delays associated with write and read clocks are determined by certain gate times, write or read register switching times, comparator speeds and gate latching speeds without the need to use subtractors to detect differences between read and write counter values.
In one aspect of the invention, a method and associated system are implemented to allow reprogramming of N and M offset values, even after writes and/or reads have been performed. If reprogramming the offsets causes a different state on PAE or PAF, the new state is calculated at the time of reprogramming and the flag output updated.
In still another aspect of the invention, a method and associated structure are implemented using a simple binary subtracter to calculate a new flag state, thereby eliminating the need to use gray-code.
In yet another aspect of the invention, a method and associated structure are implemented using a combination of gates, read/write register, comparators and latch gates to eliminate the need for subtracters to detect differences between read and write counters.
Still another aspect of the invention is associated with a system and method implemented to provide a pair of status flags which switch in a short amount of time relative to an external clock and that can be reprogrammed multiple times, even after FIFO writes and reads have occurred.